1. Field of the Invention
The present invention is related to a flip-flop circuit. More particularly, it is related to a master-slave type flip-flop circuit having a scanning function which is used in a post-manufacture test of an integrated circuit (IC) containing the master-slave type flip-flop circuit.
2. Description of the Related Art
The master-slave type flip-flop circuit (below; master-slave FF) is constituted by two flip-flop circuits, i.e., a master flip-flop (master stage) and a slave flip-flop (slave stage). The master stage and the slave stage circuits have a similar arrangement and are activated by the leading edge and trailing edge of clock signals. Consequently, many master-slave FF's are provided as internal circuits of an IC together with many gate circuits.
Circuits having a scanning function are used for testing the internal circuits of the IC, and each of these scanning function circuits is added to each of the master-slave FF's. Accordingly, the performance test of the IC is achieved by testing the master-slave FF through the scanning function.
Conventionally, the scanning function circuit arrangement is provided at an external portion of each master-slave FF arrangement, but this external circuit has the following problems, i.e., the circuit arrangement is complicated, power consumption is large, and the operation speed is slow.